Many computing devices include integrated circuits that utilize a synchronous design model. Synchronous designs typically undergo time discretization during early stages of design. This may result in early design decisions being made based on fixed latencies of computation and communication. These early design decisions may prevent changes during later design stages and create difficulties in scaling the design to fit advanced technologies. This is due, in some instances, to disproportional scaling of wire delays with respect to computing device delays.
In nano-scale technologies, for example, calculating the number of cycles required to transmit an event from a sender to a receiver may not be solvable until the final layout has been generated. This often leads to a significant re-design after the first layout is done. It may also lead to re-pipelining after the design is scaled into an advanced technology. Iterating and re-pipelining, however, are reactive rather than proactive solutions.